fs_mf_g_h_decode.vhd

来自「thats the CPU source made by JI FENG」· VHDL 代码 · 共 44 行

library ieee;
use ieee.std_logic_1164.all;

entity decode is
  
  port (
    fs : in  std_logic_vector(3 downto 0);
    MFsel : out std_logic;
    Gsel  : out std_logic_vector(3 downto 0);
    Hsel  : out std_logic_vector(1 downto 0));

end decode;

architecture rtl of decode is
  signal FS_decoded : std_logic_vector(6 downto 0);
begin

  process(fs)

  begin
    case fs is
      when "0000" => FS_decoded <= "00000--";
      when "0001" => FS_decoded <= "00001--";
      when "0010" => FS_decoded <= "00010--";
      when "0100" => FS_decoded <= "00100--";
      when "0101" => FS_decoded <= "00101--";
      when "0110" => FS_decoded <= "00110--";
      when "0111" => FS_decoded <= "00111--";
      when "1000" => FS_decoded <= "01-00--";
      when "1001" => FS_decoded <= "01-01--";
      when "1010" => FS_decoded <= "01-10--";
      when "1011" => FS_decoded <= "01-11--";
      when "1100" => FS_decoded <= "1----00";
      when "1101" => FS_decoded <= "1----01";
      when "1110" => FS_decoded <= "1----10";

      when others => null;
    end case;
  end process;
  MFsel <= FS_decoded(6);
  Gsel  <= FS_decoded(5 downto 2);
  Hsel  <= FS_decoded(1 downto 0);
end rtl;