muxd_md.vhd

来自「thats the CPU source made by JI FENG」· VHDL 代码 · 共 28 行

library ieee;
use ieee.std_logic_1164.all;

entity MUXD is
  
  port (
    DATA_in : in std_logic_vector(15 downto 0);
    F           : in std_logic_vector(15 downto 0);
    MD         : in std_logic;
    BUS_D      : out std_logic_vector(15 downto 0));

end MUXD;


architecture rtl of MUXD is

begin  -- rtl
process(DATA_in,F,MD)
  begin
    case MD is
      when '0' => BUS_D<= F;
      when '1'=> BUS_D<=DATA_in;
      when others => null;
    end case;
  end process;

end rtl;