extend.vhd

来自「thats the CPU source made by JI FENG」· VHDL 代码 · 共 21 行

library ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_signed.ALL;
USE ieee.std_logic_unsigned.ALL;
entity EXTEND is
  
  port (
    data_mem     : in  std_logic_vector(15 downto 0);
    extend_out   : out std_logic_vector(15 downto 0);
    zerofill_out : out std_logic_vector(15 downto 0));

end EXTEND;

architecture rtl of EXTEND is
begin  -- rtl
extend_out<= "1111111111" & data_mem(8 downto 6) & data_mem(2 downto 0);
zerofill_out<="0000000000000"&data_mem(2 downto 0);  

end rtl;