instruction_memory.vhd

来自「thats the CPU source made by JI FENG」· VHDL 代码 · 共 41 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity instruction_memory is

  port (

    addrin  : in  std_logic_vector(15 downto 0) := (others => '0');
    mem_out : out std_logic_vector(15 downto 0));

end instruction_memory;

architecture bhv of instruction_memory is
  
  type table9x16 is array (0 to 8) of std_logic_vector(15 downto 0);
  signal ram1 : table9x16;
begin  -- bv
  process(addrin)

  begin
    

    ram1 (0) <= "0000101001010011";

    ram1 (1) <= "0100000000100101";

    ram1 (2) <= "1000010010111011";

    ram1 (3) <= "1100000111110110";

    ram1 (4) <= "0000000001100000";
    
    

    mem_out <= ram1(conv_integer(addrin));

  end process;
end bhv;