bit_logic_circuit.vhd

来自「thats the CPU source made by JI FENG」· VHDL 代码 · 共 29 行

library ieee;
use ieee.std_logic_1164.all;

entity bit_logic_circuit is
  
  port (
    A  : in std_logic;
    B  : in std_logic; 
    S0 : in std_logic;
    S1 : in std_logic;
    G  : out std_logic);
end bit_logic_circuit;

architecture rtl of bit_logic_circuit is
signal S : std_logic_vector(1 downto 0);
begin  -- rtl
 S <= S1 & S0;
process(S,A,B)
begin
  case S is
    when "00" => G<=A and B ;
    when "01" => G<= A or B;
    when "10" => G<= A xor B;
    when "11" => G<= not(A);
    when others => null;
  end case;
end PROCESS;
end rtl;