tb_cpu.vhd

来自「thats the CPU source made by JI FENG」· VHDL 代码 · 共 31 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity tb_cpu is
  
end tb_cpu;

architecture tb of tb_cpu is

component cpu
  port (
    clk   : in std_logic;
    reset : in std_logic);
end component;

signal tb_clk : std_logic := '0';
signal tb_reset : std_logic := '1';
begin  -- tb


ucpu : cpu port map (
  clk   => tb_clk,
  reset => tb_reset);

tb_clk <= not tb_clk after 50 ns;
tb_reset <='0' after 100 ns;

end tb;