shift_2.vhd

来自「thats the CPU source made by JI FENG」· VHDL 代码 · 共 27 行

library ieee;
use ieee.std_logic_1164.all;


entity shift_1 is
  generic (N : integer := 16);
  port (Hsel : in  std_logic_vector(1 downto 0);
        B    : in  std_logic_vector (N-1 downto 0);
        H    : out std_logic_vector (N-1 downto 0));
end shift_1;

architecture rtl of shift_1 is
begin
  process(Hsel,B)
  begin
    case Hsel is

      when "00"   => H <= B;
      when "01"   => H <= '0' & B(N-1 downto 1);  -- shift right
      when "10"   => H <= B(N-2 downto 0) &'0';   -- shift left;
      when others => null;
    end case;
  end process;
  
end rtl;