datamemory.vhd

来自「thats the CPU source made by JI FENG」· VHDL 代码 · 共 33 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity ram is
  port
    (
      clk        : in  std_logic;
      data_in          : in  std_logic_vector(15 downto 0);
      address  : in  std_logic_vector(15 downto 0);
      MW            : in  std_logic;
      data_out             : out std_logic_vector(15 downto 0)
      );
end ram;

architecture rtl of ram is
  type RAM is array(0 to 2 ** 15) of std_logic_vector(15 downto 0);

  signal ram_block : RAM;
begin
  process (clk)
  begin
    if (clk'event and clk = '1') then
      if (MW = '1') then
        ram_block(conv_integer(address)) <= data_in;
      end if;
       
      Data_out <= ram_block(conv_integer(address));
    end if;
  end process;
end rtl;