mux_shifter.vhd

来自「thats the CPU source made by JI FENG」· VHDL 代码 · 共 29 行

library ieee;
use ieee.std_logic_1164.all;

entity MUX_shifter is
  
  port (
    S  : in  std_logic_vector(1 downto 0);
    P0 : in  std_logic;
    P1 : in  std_logic;
    P2 : in  std_logic;
    B  : in  std_logic;
    H  : out std_logic);

end MUX_shifter;

architecture rtl of MUX_shifter is
begin

  process(S)
  begin
    case S is
      when "00"   => H <= B;
      when "01"   => H <= p1;
      when "10"   => H <= P2;
      when others => null;
    end case;
  end process;
end rtl;