pc_counter.vhd

thats the CPU source made by JI FENG

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity PC is
  
  port (
    clk    : in  std_logic;
    reset  : in  std_logic;
    PL     : in  std_logic;
    JB     : in  std_logic;
    BC     : in  std_logic;
    AD     : in  std_logic_vector(15 downto 0);
    EXTEND : in  std_logic_vector(15 downto 0);
    PC     : out std_logic_vector(15 downto 0));

end PC;

architecture rtl of PC is
------------------------------------------------------------signal PL_JB_BC : std_logic_vector(2 downto 0);
signal PC_tmp : std_logic_vector(15 downto 0):="0000000000000000";  

begin  -- rtl
--------------------------------------------------------------PL_JB_BC <= PL & JB & BC;
  process(clk,PC_tmp)
  begin
    
   if reset = '1' then
        PC_tmp <=(others =>'0');
   
   elsif  clk'event and clk = '1'  then
      
 ----------------------------------------------------------  case PL_JB_BC is 
 ---------------------------------------------------------  	when "0--"=> pc_tmp <= pc_tmp + '1';
 ----------------------------------------------------------   when "11-"=> pc_tmp <= "0000000000000111";
 ----------------------------------------------------------  	--when "11-"=> pc_tmp <= pc_tmp + AD ;
 ----------------------------------------------------------  	when "100"=> pc_tmp <= pc_tmp + EXTEND;
 ----------------------------------------------------------   when "101"=> pc_tmp <= pc_tmp + EXTEND;
 ----------------------------------------------------------   when others=> null; 
 ----------------------------------------------------------   end case;
 ----------------------------------------------------------  end if;
 ----------------------------------------------------------  end process;
       --Update PC
      if PL = '0' then
        PC_tmp <= PC_tmp + '1';
  
      elsif PL = '1' then
       	if JB = '1' then
					 PC_tmp <= PC_tmp + AD;               --JUMP

       	elsif JB = '0' then
                                               -- Conditional branch
         	if BC = '0' then
           	PC_tmp <= PC_tmp + EXTEND;          --           conditional branch on ZERO
         	elsif BC = '1' then
           	PC_tmp <= PC_tmp+ EXTEND;    --                   conditional branch on negative
         	end if;
       	end if;
     	end if;
   	end if;
end process;
PC <= PC_tmp;
end rtl;