4_bit_parallel adder.vhd

thats the CPU source made by JI FENG

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

use ieee.std_logic_arith.all;

entity bit_adder is
  port (
    A    : in  std_logic;
    B    : in  std_logic;
    S0   : in  std_logic;
    S1   : in  std_logic;
    Cin  : in  std_logic;
    G    : out std_logic;
    Cout : out std_logic);

end bit_adder;

architecture rtl of bit_adder is
  component b_input_logic
    port (
      B  : in  std_logic;
      S0 : in  std_logic;
      S1 : in  std_logic;
      Y  : out std_logic);
  end component;

  signal sel   : std_logic_vector(2 downto 0);
  signal Y_tmp : std_logic;
begin  -- rtl
  sel <= S1&S0&cin;

  u_b_input_logic : b_input_logic port map (
    B  => B,
    S0 => S0,
    S1 => S1,
    Y  => Y_tmp);

  --G    <= A xor Y_tmp xor Cin;
  cout <= ((A and Y_tmp) or (A and cin)) or (Y_tmp and cin);



  process (sel,y_tmp,A)
  begin  -- process
    
    case sel is
      when "000"  => G <= A;
      when "001"  => G <= A xor '1';
      when "010"  => G <= A xor y_tmp;
      when "011"  => G <= A xor y_tmp xor '1';
      when "100"  => G <= A xor y_tmp ;
      when "101"  => G <= A xor y_tmp  xor '1';
      when "110"  => G <= A xor y_tmp;
      when "111"  => G <= A;
      when others => null;
    end case;
  end process;
  
end rtl;