b_input logic.vhd

来自「thats the CPU source made by JI FENG」· VHDL 代码 · 共 32 行

--this part is made for the B_INPUT_LOGIC.
library ieee;
use ieee.std_logic_1164.all;

entity b_input_logic is
  
  port (
    B  : in  std_logic;
    S0 : in  std_logic;
    S1 : in  std_logic;
    Y  : out std_logic);
end b_input_logic;

architecture rtl of b_input_logic is

  signal S : std_logic_vector(1 downto 0);
begin  -- rtl
  
  S<=S1&S0;
PROCESS(B,S)
  BEGIN
  case S is
    when "00"   => y <= '0';
    when "01"   => y <= B;
    when "10"   => y <= not(B) ;
    when "11"   => y <= '1';
    when others => null;
  end case;
end PROCESS;

end rtl;