muxf.vhd

来自「thats the CPU source made by JI FENG」· VHDL 代码 · 共 27 行

library ieee;
use ieee.std_logic_1164.all;

entity MUXF is
  
  port (
    MUXF_0     : in  std_logic_vector(15 downto 0);
    MUXF_1     : in  std_logic_vector(15 downto 0);
    MFsel : in  std_logic;
    F     : out std_logic_vector(15 downto 0));
end MUXF;

architecture rtl of MUXF is

begin  -- rtl

  process(MUXF_0,MUXF_1,MFsel)
    begin
    case MFsel is
      when '0' => F<=MUXF_0 ;
      when '1' => F<=MUXF_1;
      when others => null;
    end case;
  end process;

    end rtl;