branch_control.vhd

thats the CPU source made by JI FENG

library ieee;
use ieee.std_logic_1164.all;

entity branch_control is
  
  port (
    V, C, N, Z             : in  std_logic;
    PL, JB, BC             : in  std_logic;
    PL_tmp, JB_tmp, BC_tmp : out std_logic);

end branch_control;


architecture rtl of branch_control is

begin  -- rtl
process(N,Z,PL,JB,BC)
  begin
  PL_tmp <= PL;
  JB_tmp <= JB;
  if N = '1' and BC ='1' then
    BC_tmp <= '1';
  elsif Z = '1' and BC ='0' then
    BC_tmp <= '0';
  else
    BC_tmp <= 'Z';
    end if;
end process;
  
end rtl;