control_all.vhd

thats the CPU source made by JI FENG

library ieee;
use ieee.std_logic_1164.all;

entity controller is
  
  port (
    clk          : in  std_logic;
    reset        : in  std_logic;
    BUSA         : in  std_logic_vector(15 downto 0);
    V, C, N, Z   : in  std_logic;
    DA,BA,AA     : out std_logic_vector(2 downto 0);
    MB,MD,RW,MW  : out std_logic;
    FS           : out std_logic_vector(3 downto 0);
    zerofill_out : out std_logic_vector(15 downto 0));
end controller;

architecture rtl of controller is

  component PC
    port (
      CLK        : in  std_logic;
      reset      : in  std_logic;
      PL, JB, BC : in  std_logic;
      AD         : in  std_logic_vector(15 downto 0);
      EXTEND     : in  std_logic_vector(15 downto 0);
      PC         : out std_logic_vector(15 downto 0));
  end component;

  component instruction_decoder
    port (
      data_in            : in  std_logic_vector(15 downto 0);
      DA, AA, BA         : out std_logic_vector(2 downto 0);
      MB                 : out std_logic;
      fs                 : out std_logic_vector(3 downto 0);
      MD                 : out std_logic;
      RW, MW, PL, JB, BC : out std_logic);
  end component;

  component instruction_memory
    port (
      addrin  : in  std_logic_vector(15 downto 0);
      mem_out : out std_logic_vector(15 downto 0));
  end component;


  component branch_control
    port (
      V, C, N, Z             : in  std_logic;
      PL, JB, BC             : in  std_logic;
      PL_tmp, JB_tmp, BC_tmp : out std_logic);
  end component;

  component EXTEND
    port (
      data_mem     : in  std_logic_vector(15 downto 0);
      extend_out   : out std_logic_vector(15 downto 0);
      zerofill_out : out std_logic_vector(15 downto 0));
  end component;

  signal mem_decode          : std_logic_vector(15 downto 0);
  signal pc_instruction      : std_logic_vector(15 downto 0);
  signal extend_tmp          : std_logic_vector(15 downto 0);
  signal PL_pc, JB_pc, BC_pc : std_logic;
 -- signal DA,BA,AA : std_logic_vector(2 downto 0);
  signal PL,JB,BC : std_logic;
 -- signal fs : std_logic_vector(3 downto 0);
  


begin  -- rtl

  uPC : pc port map (
    clk    => clk,
    reset  => reset,
    PL     => PL_pc,
    JB     => JB_pc,
    BC     => BC_pc,
    AD     => BUSA,
    EXTEND => extend_tmp,
    PC     => pc_instruction);


  
  uinstruction_decoder : instruction_decoder port map (
    Data_in => mem_decode,
    DA      => DA,
    BA      => BA,
    AA      => AA,
    MB      => MB,
    fs      => fs,
    MD      => MD,
    RW      => RW,
    MW      => MW,
    PL      => PL,
    JB      => JB,
    BC      => BC);

  uinstruction_memory : instruction_memory port map (
    addrin  => PC_instruction,
    mem_out => mem_decode);

  ubranch_control : branch_control port map (
    V      => V,
    C      => C,
    N      => N,
    Z      => Z,
    PL     => PL,
    JB     => JB,
    BC     => BC,
    PL_tmp => PL_pc,
    JB_tmp => JB_pc,
    BC_tmp => BC_pc);


  uextend : EXTEND port map (
    data_mem     => mem_decode,
    extend_out   => extend_tmp,
    zerofill_out => zerofill_out);



  
end rtl;