top_all.vhd

thats the CPU source made by JI FENG

library ieee;
use ieee.std_logic_1164.all;

entity CPU is
  
  port (
    clk   : in std_logic;
    reset : in std_logic);

end CPU;

architecture rtl of CPU is

  component controller
    port (
      clk            : in  std_logic;
      reset          : in  std_logic;
      BUSA           : in  std_logic_vector(15 downto 0);
      V, C, N, Z     : in  std_logic;
      DA, BA, AA     : out std_logic_vector(2 downto 0);
      MB, MD, RW, MW : out std_logic;
      fs             : out std_logic_vector(3 downto 0);
      zerofill_out   : out std_logic_vector(15 downto 0));
  end component;

  component TOP1
    port (
      clk             : in  std_logic;
      AA, BA, DA      : in  std_logic_vector(2 downto 0);
      RW              : in  std_logic;
      constant_in     : in  std_logic_vector(15 downto 0);
      MB              : in  std_logic;
      fs              : in  std_logic_vector(3 downto 0);
      MD              : in  std_logic;
      BUSA            : out  std_logic_vector(15 downto 0);
      V, C, N, Z      : out std_logic;
      MW              : in  std_logic);
  end component;



  signal BUSA_tmp                                                   : std_logic_vector(15 downto 0);
  signal zerofill_out_tmp                                           : std_logic_vector(15 downto 0);
  signal DA_tmp, BA_tmp, AA_tmp                                     : std_logic_vector(2 downto 0);
  signal MB_tmp, MD_tmp, RW_tmp, MW_tmp, V_tmp, C_tmp, N_tmp, Z_tmp : std_logic;
  signal fs_tmp                                                     : std_logic_vector(3 downto 0);
  
begin
  ucontroller : controller port map (
    clk          => clk,
    reset        => reset,
    BUSA         => BUSA_tmp,
    DA           => DA_tmp,
    BA           => BA_tmp,
    AA           => AA_tmp,
    MB           => MB_tmp,
    MD           => MD_tmp,
    RW           => RW_tmp,
    MW           => MW_tmp,
    fs           => fs_tmp,
    V            => V_tmp,
    C            => C_tmp,
    N            => N_tmp,
    Z            => Z_tmp,
    zerofill_out => zerofill_out_tmp);

  uTOP1 : TOP1 port map (
    clk             => clk,
    AA              => AA_tmp,
    BA              => BA_tmp,
    DA              => DA_tmp,
    RW              => RW_tmp,
    constant_in     => zerofill_out_tmp,
    BUSA => BUSA_tmp,
    MB              => MB_tmp,
    fs              => fs_tmp,
    MD              => MD_tmp,
    V               => V_tmp,
    C               => C_tmp,
    N               => N_tmp,
    Z               => Z_tmp,
    MW              => MW_tmp);

end rtl;