instruction_decode.vhd

thats the CPU source made by JI FENG

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity instruction_decoder is
  
  port (
    Data_in: in std_logic_vector(15 downto 0);
    DA     : out std_logic_vector(2 downto 0);
    BA     : out std_logic_vector(2 downto 0);
    AA     : out std_logic_vector(2 downto 0);
    MB     : out std_logic;
    FS     : out std_logic_vector(3 downto 0);
    MD     : out std_logic;
    RW     : out std_logic;
    MW     : out std_logic;
    PL     : out std_logic;
    JB     : out std_logic;
    BC     : out std_logic);

end instruction_decoder;

architecture rtl of instruction_decoder is

  signal result : std_logic_vector(6 downto 0);
  signal data_in_tmp1 : std_logic_vector(2 downto 0);
  signal data_in_tmp2 : std_logic_vector(3 downto 0);
begin  -- rtl
 data_in_tmp1<= data_in(15 downto 13);
 data_in_tmp2 <=data_in(15 downto 13) & data_in(9);
 
  process(data_in_tmp1,data_in_tmp2)
  begin
    case data_in_tmp1 is
      when "000" => result<= "00100--";
      when "001"=>  result<= "01100--";
      when "010"=>  result<= "0-010--";
      when "100"=>  result<= "10100--";
      when "111"=>  result<= "--0011-";
      when others => null;
    end case;

    case data_in_tmp2 is
      when "1100"=>  result<= "--00100";
      when "1101"=>  result<= "--00101";
      when others => null;
     end case;
   end process;  
  
  DA<=data_in(8 downto 6);
  AA<=data_in(5 downto 3);
  BA<=data_in(2 downto 0);
  MB<=result(6);
  FS<=data_in(12 downto 9);
  MD<=result(5);
  RW<=result(4);
  MW<=result(3);
  PL<=result(2);
  JB<=result(1);
  BC<=result(0);  
  end rtl;