top1.vhd

thats the CPU source made by JI FENG

library ieee;
use ieee.std_logic_1164.all;

entity TOP1 is
  
  port (
    clk         : in  std_logic;
    AA, BA, DA  : in  std_logic_vector(2 downto 0);
    RW          : in  std_logic;
    constant_in : in  std_logic_vector(15 downto 0);
    MB          : in  std_logic;        -- FS
    FS          : in  std_logic_vector(3 downto 0);
    MD          : in  std_logic;
    BUSA        : out std_logic_vector(15 downto 0);
    V, C, N, Z  : out std_logic;
    MW          : in  std_logic); 

end TOP1;

architecture rtl of TOP1 is

  component regfile
    port (
      clk        : in  std_logic;
      AA, BA, DA : in  std_logic_vector(2 downto 0);
      RW         : in  std_logic;
      D          : in  std_logic_vector(15 downto 0);
      A, B       : out std_logic_vector(15 downto 0));
  end component;

  component function_unit
    port (
      fs         : in  std_logic_vector(3 downto 0);
      A, B       : in  std_logic_vector(15 downto 0);
      V, C, N, Z : out std_logic;
      F          : out std_logic_vector(15 downto 0));
  end component;

  component MUXB
    port (
      constant_in : in  std_logic_vector(15 downto 0);
      B_data      : in  std_logic_vector(15 downto 0);
      MB          : in  std_logic;
      BUS_B       : out std_logic_vector(15 downto 0));
  end component;

  component MUXD
    port (
      DATA_in : in  std_logic_vector(15 downto 0);
      F       : in  std_logic_vector(15 downto 0);
      MD      : in  std_logic;
      BUS_D   : out std_logic_vector(15 downto 0));
  end component;

  component RAM
    port (
      clk      : in  std_logic;
      data_in  : in  std_logic_vector(15 downto 0);
      address  : in  std_logic_vector(15 downto 0);
      MW       : in  std_logic;
      data_out : out std_logic_vector(15 downto 0));
  end component;
  

  signal MUXD_Ddata  : std_logic_vector(15 downto 0);
  signal BUSA_tmp : std_logic_vector(15 downto 0);
  signal Bdata_MUXB  : std_logic_vector(15 downto 0);
  signal MUXB_B      : std_logic_vector(15 downto 0);
  signal F_MUXD      : std_logic_vector(15 downto 0);
  signal Data_out_MUD1 : std_logic_vector(15 downto 0);

begin
  
  BUSA<=BUSA_tmp;
  
  uregfile : regfile port map (
    clk => clk,
    AA  => AA,
    BA  => BA,
    DA  => DA,
    RW  => RW,
    D   => MUXD_Ddata,
    A   => BUSA_tmp,
    B   => Bdata_MUXB);

  ufunction_unit : function_unit port map (
    fs => fs,
    A  => BUSA_tmp,
    B  => MUXB_B,
    V  => V,
    C  => C,
    N  => N,
    Z  => Z,
    F  => F_MUXD);

  uMUXB : MUXB port map (
    constant_in => constant_in,
    B_data      => Bdata_MUXB,
    MB          => MB,
    BUS_B       => MUXB_B);


  uMUXD : MUXD port map (
    DATA_in =>  Data_out_MUD1,
    F       => F_MUXD,
    MD      => MD,
    BUS_D   => MUXD_Ddata);

  Uram : RAM port map (
    clk => clk,
    MW  => MW,
    data_out => Data_out_MUD1,
    data_in    => MUXB_B,
    address => BUSA_tmp);
end rtl;