top_16bit_adder.vhd

thats the CPU source made by JI FENG

library IEEE;
use IEEE.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;


entity rip_adder is
  port(A, B       : in  std_logic_vector(15 downto 0);
       S2, S1, S0 : in  std_logic;
       cin        : in  std_logic;
       G          : out std_logic_vector(15 downto 0);
       V          : out std_logic;
       N          : out std_logic;
       Z          : out std_logic;
       C          : out std_logic);
end rip_adder;

architecture behave of rip_adder is

  component bit_adder
    port(A, B   : in  std_logic;
         S0, S1 : in  std_logic;
         Cin    : in  std_logic;
         G      : out std_logic;
         Cout   : out std_logic);
  end component;

  component bit_logic_circuit
    port (
      A  : in  std_logic;
      B  : in  std_logic;
      S0 : in  std_logic;
      S1 : in  std_logic;
      G  : out std_logic);
  end component;

  component mux2_1
    port (
      port1 : in  std_logic;
      port2 : in  std_logic;
      Sel   : in  std_logic;
      Gout  : out std_logic);
  end component;

  signal carry   : std_logic_vector(16 downto 0);
  signal G_arith : std_logic_vector(15 downto 0);
  signal G_logic : std_logic_vector(15 downto 0);
  signal sel_4   : std_logic_vector(3 downto 0);

begin

  sel_4    <= S2&S1&S0&Cin;
  carry(0) <= cin;
  C        <= carry(16);

  g1 : for i in 0 to 15 generate

    ubit_add : bit_adder port map(A    => A(i),
                                  B    => B(i),
                                  S0   => S0,
                                  S1   => S1,
                                  cin  => carry(i),
                                  G    => G_arith(i),
                                  Cout => carry(i+1));

    ubit_logic_circuit : bit_logic_circuit port map (
      A  => A(i),
      B  => B(i),
      S0 => Cin,
      S1 => S0,
      G  => G_logic(i));

    umux2_1 : mux2_1 port map (
      port1 => G_arith(i),
      port2 => G_logic(i),
      Sel   => S2,
      Gout  => G(i));
  end generate g1;

  process(S2,G_arith,G_logic)
  begin
       if S2 = '0' then
         N <=G_arith(15);
         V <=G_arith(15) xor Carry(16);
         if G_arith = "0000000000000000" then
           Z <='1';
         else
            Z<='0';
         end if;
       elsif S2 = '1' then
         N <=G_logic(15);
         V <=G_logic(15) xor Carry(16);
         if G_logic = "0000000000000000" then
           Z <='1';
         else
           Z<='0';
         end if;
       end if;
  end process;
--  process (sel)
--  begin  -- process

--    case sel is
-- when "0000" => G <= A;

-- when "0001" => G <= A + 1;

-- when "0010" => G <= A + B;

-- when "0011" => G <= A+B+1;

-- when "0100" => G <= A-B-1;

-- when "0101" => G <= A-B;

-- when "0110" => G <= A-1;

-- when "0111" => G <= A;

  -- when "1-00" => G = A and B;

-- when "1-01" => G = A or B;
-- when "1-10" => G = A xor B;
-- when "1-11" => G = not(A);
-- when others => null;
--    end case;
--  end process;
  

end behave;