register.vhd

来自「thats the CPU source made by JI FENG」· VHDL 代码 · 共 95 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.STD_LOGIC_ARITH.all;
USE IEEE.STD_LOGIC_UNSIGNED.all;

ENTITY regfile IS

PORT(
clk: IN std_logic;
AA, BA , DA:			IN  std_logic_vector(2 DOWNTO 0); 
RW				 :   		in  std_logic;                    	--'1' then read.
                                        					  	--'0' then write;
D				   :      IN  std_logic_vector(15 DOWNTO 0);
A, B			 :      OUT std_logic_vector(15 DOWNTO 0)); --RFcout

END regfile;

ARCHITECTURE rtl of regfile IS

signal reg0: std_logic_vector(15 downto 0) :="0000000000001000";
signal reg1: std_logic_vector(15 downto 0) :="0000000000000100";
signal reg2: std_logic_vector(15 downto 0) :="0000000000000011";
signal reg3: std_logic_vector(15 downto 0) :="0000000000000001";
signal reg4: std_logic_vector(15 downto 0) :="0000000001000110";
signal reg5: std_logic_vector(15 downto 0) :="0000000001010001";
signal reg6: std_logic_vector(15 downto 0) :="0000000000000000";
signal reg7: std_logic_vector(15 downto 0) :="0000000000000111";

BEGIN


PROCESS (clk,DA,RW)--reg0,reg1, reg2, reg3,reg4, reg5, reg6, reg7) --WRITE PROCESS --wRFB
BEGIN
IF RW='0' or RW='1' then                 ---attention
if clk='1' and clk'event THEN
                                      
CASE DA IS
WHEN "000" => reg0 <= D;
WHEN "001" => reg1 <= D;
WHEN "010" => reg2 <= D;
WHEN "011" => reg3 <= D;
WHEN "100" => reg4 <= D;
WHEN "101" => reg5 <= D;
WHEN "110" => reg6 <= D;
WHEN "111" => reg7 <= D;
WHEN others => NULL;
end case;
END IF;
END IF;
END PROCESS;


PROCESS (AA ,RW,reg0,reg1, reg2, reg3,reg4, reg5, reg6, reg7) --READ PROCESS
BEGIN
--IF clk 'EVENT AND clk= '1' THEN
IF RW = '1' THEN
CASE AA IS
WHEN "000" => A <= reg0;
WHEN "001" => A <= reg1;
WHEN "010" => A <= reg2;
WHEN "011" => A <= reg3;
WHEN "100" => A <= reg4;
WHEN "101" => A <= reg5;
WHEN "110" => A <= reg6;
WHEN "111" => A <= reg7;
WHEN OTHERS => A <= "XXXXXXXXXXXXXXXX";
END CASE;
END IF;
--END IF;
END PROCESS;



PROCESS (BA,RW,reg0,reg1, reg2, reg3,reg4, reg5, reg6, reg7) --READ PROCESS
BEGIN
--IF clk 'EVENT AND clk= '1' THEN
IF RW = '1' THEN

CASE BA IS
WHEN "000" => B <= reg0;
WHEN "001" => B <= reg1;
WHEN "010" => B <= reg2;
WHEN "011" => B <= reg3;
WHEN "100" => B <= reg4;
WHEN "101" => B <= reg5;
WHEN "110" => B <= reg6;
WHEN "111" => B <= reg7;
WHEN OTHERS => B <= "XXXXXXXXXXXXXXXX";
END CASE;
--END IF;
END IF;
END PROCESS;

END rtl;