function_unit.vhd

thats the CPU source made by JI FENG

library ieee;
use ieee.std_logic_1164.all;

entity function_unit is
  
  port (
    FS   : in  std_logic_vector(3 downto 0);
    A, B : in  std_logic_vector(15 downto 0);
    V    : out std_logic;
    C    : out std_logic;
    N    : out std_logic;
    Z    : out std_logic;
    F    : out std_logic_vector(15 downto 0));
end function_unit;

architecture rtl of function_unit is

  component rip_adder
    port (
      A, B       : in  std_logic_vector(15 downto 0);
      S2, S1, S0 : in  std_logic;
      Cin        : in  std_logic;
      V, N, Z, C : out std_logic;
      G          : out std_logic_vector(15 downto 0));
  end component;

  component shift_1
    port (
      Hsel : in  std_logic_vector(1 downto 0);
      B    : in  std_logic_vector(15 downto 0);
      H    : out std_logic_vector(15 downto 0));
  end component;

  component MUXF
    port (
      MUXF_0 : in  std_logic_vector(15 downto 0);
      MUXF_1 : in  std_logic_vector(15 downto 0);
      MFsel  : in  std_logic;
      F      : out std_logic_vector(15 downto 0));
  end component;

  component decode
    port (
      fs    : in  std_logic_vector(3 downto 0);
      MFsel : out std_logic;
      Gsel  : out std_logic_vector(3 downto 0);
      Hsel  : out std_logic_vector(1 downto 0));
  end component;



  signal Gsel   : std_logic_vector(3 downto 0);
  signal Hsel   : std_logic_vector(1 downto 0);
  signal MFsel  : std_logic;
  signal G_tmp      : std_logic_vector(15 downto 0);
  --signal H      : std_logic_vector(15 downto 0);
  --signal MUXF_0 : std_logic_vector(15 downto 0);
  signal MUXF_1_H : std_logic_vector(15 downto 0);
begin  -- rtl

  urip_adder : rip_adder port map (
    A   => A,
    B   => B,
    S2  => Gsel(3),
    S1  => Gsel(2),
    S0  => Gsel(1),
    Cin => Gsel(0),
    V   => V,
    N   => N,
    Z   => Z,
    C   => C,
    G   => G_tmp);

  ushift_a : shift_1 port map (
    Hsel => Hsel,
    B    => B,
    H    => MUXF_1_H);

  uMUXF : MUXF port map (
    MUXF_0 => G_tmp,
    MUXF_1 => MUXF_1_H,
    MFsel  => MFsel,
    F      => F);


  udecode : decode port map (
    fs    => fs,
    MFsel => MFsel,
    Gsel  => Gsel,
    Hsel  => Hsel);
end rtl;