mux2_1.vhd

thats the CPU source made by JI FENG

library ieee;
use ieee.std_logic_1164.all;

entity mux2_1 is
  
  port (
    port1 : in  std_logic;
    port2 : in  std_logic;
    Sel   : in  std_logic;
    Gout  : out std_logic);

end mux2_1;

architecture rtl of mux2_1 is

begin  -- rtl
process(sel,port1,port2)
  begin
  case sel is
    when'0' => Gout <= port1 ;
    when '1' => Gout <= port2;
    when others => null;
  end case;
end process;

end rtl;