fdivision_tb.v.bak

来自「verilog分频器～时钟为50hmz」· BAK 代码 · 共 17 行

`timescale 1ns/1ns
`include "./fdivision.v"
module fdivision_tb;
    reg RESET,f10m;
    wire f500k;
    always #10 f10m=~f10m;
    initial
    begin
    f10m=0;
   RESET=1;
    #10 RESET=0;
    #100 RESET=1;
    #10000 $stop;
end
fdivision m(.RESET(RESET),.f10m(f10m),.f500k(f500k));
endmodule