fdivision_tb.v

来自「verilog分频器～时钟为50hmz」· Verilog 代码 · 共 17 行

`timescale 1ns/1ns
`include "./fdivision.v"
module fdivision_tb;
    reg RESET,F10M;
    wire F500K;
    always #10 F10M=~F10M;
    initial
    begin
   F10M=0;
   RESET=1;
    #10 RESET=0;
    #100 RESET=1;
    #10000 $stop;
end
fdivision m(.RESET(RESET),.F10M(F10M),.F500K(F500K));
endmodule