demo_multiout_function.v

该代码中有不少关于学习verilog HDL的例子,对初学者有帮助

module demo_multiout_function;
reg[7:0] a,b,c,d;
initial  
  begin
    a=8'h54;
    b=8'h32;
    {c,d}=multiout_fun(a,b);
    $display("the value of c is:%b;d is:%b",c,d);
  end
function multiout_fun;
input[7:0] in1;
input[7:0] in2;
reg[7:0] out1;
reg[7:0] out2;
begin
  out1=in1&in2;
  out2=in1|in2;
  multiout_fun={out1,out2};
end
endfunction
endmodule