ex1.v

来自「该代码中有不少关于学习verilog HDL的例子,对初学者有帮助」· Verilog 代码 · 共 23 行

module ex1;
reg[3:0] a,b;
initial
begin
  a=4'b0011;b=4'b1001;
  $display("%d %d",a,b);
  $display("%b,%b",a,b);
  $display("a=%h b=%h",a,b);
  $display("a=%o,b=%o",a,b);
  $display("a is equal to %o,b is equal to %o",a,b);
  $display("a is %o b is %o",a,b);
  $display("a is %o,b is %o",a,b);
  $display("a is %o and b is %o",a,b);
  $display("a is %o;b is %o",a,b);
  $display(a);
  $display("a");
  $display({a,b});
  $display("{a,b}");
  $displayb(a);
  $displayb({a,b});
  $displayb("a");
end
endmodule