timing_control_inner_mode.v.bak

该代码中有不少关于学习verilog HDL的例子,对初学者有帮助

module timing_control_inner_mode(b,c,d,a,clk,enable);
output b,c,d;
input a,clk,enable;
reg b,c,d;
initial
  fork
    b=0;
    c=0;
    d=0;
  join
initial
  fork
    b=#5 a;
    c=@(posedge clk) a;
    d=wait(enable)a;
  join
endmodule