control.v

该工程是基于verilog hdl 语言编写的帧传输协议HDLC帧的发送端代码

/////////////////////////////
//控制模块                 // 
/////////////////////////////
module control(clk,ept,rd,reset1,flag,en1,en2,en3,sel1,sel2);
input ept,reset1,flag,clk;
output en1,en2,en3,sel1,sel2,rd;
reg reset2,en1,en2,en3,sel1,sel2,rd;
reg[5:0] count1;
reg[3:0] count2;
reg[3:0] count3;
integer j;
always @(en2 or flag or count2 or reset1 or reset2 or count1 or count2)
begin
    
	if(!en2&&flag&&count1==48)en1=0;
	else if(!en2&&!flag&&!ept)en1=1;
	else if(count2==7&&!ept)begin
		en1=1;
		en3=0;
	end
	else if(ept&&count2>=7)begin 
		en3=1;
		en1=0;
	end
	else if(count2<=6)begin
		en3=0;
		en1=0;
	end
end
always @(posedge clk )
begin
	if(reset1||reset2)begin 
		sel1=1;
		sel2=0;
		en2=1;
		reset2<=0;
		count2=0;
	end

	else begin
		//if(ept==0)rd<=1;
		//if(ept)rd<=0;
		if(en3)begin
			en2=0;
			sel2=1;
		end
	    if(en2==1)begin
				if(count2>=0&&count2<8)
					count2=count2+1;
				else if(count2==8)begin
					en2=0;
				//	en1=1;
					sel2=1;	
				//	count2<=0;
				end
				
		end
		else if(!ept)begin
			rd<=1;
			if(en1) begin
				if(count1>=0&&count1<32)begin
					count1=count1+1;
					if(count1==32)
						sel1=0;
				end
				
				else if(count1==32)		
					count1=count1+1;
				
				else if(count1>32&&count1<48)
			    	count1<=count1+1;	
				else if(count1==48)begin
						reset2=1;
				end
				
					
				
				
					//count1<=0;
			
			end
			else if(!en1)
				count1=count1;
	 	end	
		else if(ept)begin
			 if(en3)begin
				if(count3>=0&&count3<8)
					count3<=count3+1;
				else if(count3==8)begin 
				reset2<=1;
				count3<=0;
				end
			end
		end
	end
end
endmodule			

/*always @(posedge clk or posedge reset1 or posedge reset2 or posedge flag)
begin
	if(reset1||reset2)begin 
		en1=0;
		sel1=1;
		sel2=0;
		count1=0;
		count2=0;
		count3=0;    
		en2=1;
		en3=0;
		reset2=0;
	end
	else if(flag)begin
			en1=0;
	end
	else if(ept==0) begin
		
		rd=1;
		if(en2==1)begin
			if(count2>=0&&count2<8)begin
				count2=count2+1;
				if(count2==7)
					en1=1;
				else if(count2==9)	begin
					sel2=1;	
					en2=0;
					count2=0;
				end
				
			end
			
		end
		else if(en1) begin
				if(count1>=0&&count1<32)begin
					count1=count1+1;
					if(count1==32)
						sel1=0;
				end
				else if(count1==32)		
						count1=count1+1;
					
		
				else if(count1>32&&count1<48)begin
					count1=count1+1;	
					if(count1==48)
						reset2=1;
				end
				else	
						count1=0;
		end
		else if(!en1)begin
			count1=count1;
			en1=1;
		end
	end
	else if(ept) begin
		rd=0;
		if(!en3)en2=1;
		if(en2)begin
			if(count2>=0&&count2<8)begin
				count2=count2+1;
				if(count2==8)begin	
					en3=1;
					sel2=1;
					en2=0;
				end
			end
			else if(count2==8)	count2=0;
			
		end
		else begin
			if(count3>=0&&count3<8)begin
				count3=count3+1;
				if(count3==8)begin 
					reset2=1;
					count3=0;
				end
			end
		end
	end
end	*/