hdlc.map.eqn

该工程是基于verilog hdl 语言编写的帧传输协议HDLC帧的发送端代码

--B1_reset2 is control:control1|reset2
--operation mode is normal

B1_reset2_lut_out = !B1L13 & (ept & (B1L64) # !ept & B1L44);
B1_reset2 = DFFEAS(B1_reset2_lut_out, clk, VCC, , , , , , );


--B1L41 is control:control1|always1~0
--operation mode is normal

B1L41 = B1_reset2 # reset1;


--B1_count1[5] is control:control1|count1[5]
--operation mode is normal

B1_count1[5]_lut_out = B1_count1[5] $ (B1_count1[4] & B1L2 & B1L52);
B1_count1[5] = DFFEAS(B1_count1[5]_lut_out, clk, VCC, , , , , , );


--B1_count1[4] is control:control1|count1[4]
--operation mode is normal

B1_count1[4]_lut_out = B1_count1[4] $ (B1L2 & B1L52);
B1_count1[4] = DFFEAS(B1_count1[4]_lut_out, clk, VCC, , , , , , );


--B1_count1[3] is control:control1|count1[3]
--operation mode is normal

B1_count1[3]_lut_out = B1L3;
B1_count1[3] = DFFEAS(B1_count1[3]_lut_out, clk, VCC, , B1L52, , , , );


--B1_count1[2] is control:control1|count1[2]
--operation mode is normal

B1_count1[2]_lut_out = B1_count1[2] $ (B1_count1[1] & B1_count1[0]);
B1_count1[2] = DFFEAS(B1_count1[2]_lut_out, clk, VCC, , B1L52, , , , );


--B1L7 is control:control1|always0~266
--operation mode is normal

B1L7 = B1_count1[5] & B1_count1[4] & !B1_count1[3] & !B1_count1[2];


--B1_count1[1] is control:control1|count1[1]
--operation mode is normal

B1_count1[1]_lut_out = B1_count1[1] $ B1_count1[0];
B1_count1[1] = DFFEAS(B1_count1[1]_lut_out, clk, VCC, , B1L52, , , , );


--B1_count1[0] is control:control1|count1[0]
--operation mode is normal

B1_count1[0]_lut_out = !B1_count1[0];
B1_count1[0] = DFFEAS(B1_count1[0]_lut_out, clk, VCC, , B1L52, , , , );


--B1L8 is control:control1|always0~267
--operation mode is normal

B1L8 = !B1_count1[1] & !B1_count1[0];


--B1L9 is control:control1|always0~268
--operation mode is normal

B1L9 = F1_flag & B1L7 & B1L8 & !B1_en2;


--B1L01 is control:control1|always0~269
--operation mode is normal

B1L01 = F1_flag # B1_en2;


--B1L6 is control:control1|always0~11
--operation mode is normal

B1L6 = ept # B1L9 # !B1L01 # !B1_count2[3];


--B1L11 is control:control1|always0~270
--operation mode is normal

B1L11 = B1_count2[2] & B1_count2[1] & B1_count2[0];


--B1L21 is control:control1|always0~271
--operation mode is normal

B1L21 = !ept & (B1L11 & !B1_count2[3] # !B1L01);


--B1L51 is control:control1|comb~0
--operation mode is normal

B1L51 = B1L6 & B1L21 & (!B1L9);


--B1L61 is control:control1|comb~1
--operation mode is normal

B1L61 = B1L6 & (B1L9 # !B1L21);


--B1_en1 is control:control1|en1
--operation mode is normal

B1_en1 = !B1L61 & (B1L51 # B1_en1 & !B1L6);


--B1L1 is control:control1|LessThan~356
--operation mode is normal

B1L1 = !B1_count2[3] & (!B1_count2[0] # !B1_count2[1] # !B1_count2[2]);


--B1L31 is control:control1|always0~272
--operation mode is normal

B1L31 = !B1L9 & (ept # B1L01 & !B1_count2[3]);


--B1_en3 is control:control1|en3
--operation mode is normal

B1_en3 = B1L31 & !B1L1 & ept # !B1L31 & (B1_en3);


--B1L42 is control:control1|count1[5]~336
--operation mode is normal

B1L42 = B1_en1 & !ept & (B1_en3 # !B1_en2);


--B1L2 is control:control1|add~457
--operation mode is normal

B1L2 = B1_count1[3] & B1_count1[2] & B1_count1[1] & B1_count1[0];


--B1L3 is control:control1|add~458
--operation mode is normal

B1L3 = B1_count1[3] $ (B1_count1[2] & B1_count1[1] & B1_count1[0]);


--B1L84 is control:control1|sel1~246
--operation mode is normal

B1L84 = !B1_count1[5] & B1L2 & !B1L3 & B1L94;


--D1L7 is free:free1|count[3]~540
--operation mode is normal

D1L7 = D1_count[3] & (D1_count[2] # D1_count[1] # D1_count[0]) # !D1_count[3] & D1_count[2] & D1_count[1] & D1_count[0];


--F1_count[4] is shift32:shift|count[4]
--operation mode is arithmetic

F1_count[4]_carry_eqn = F1L73;
F1_count[4]_lut_out = F1_count[4] $ (F1_count[4]_carry_eqn);
F1_count[4] = DFFEAS(F1_count[4]_lut_out, clk, VCC, , F1L04, ~GND, , , F1L93);

--F1L24 is shift32:shift|count[4]~263
--operation mode is arithmetic

F1L24 = CARRY(F1_count[4] # !F1L73);


--F1L83 is shift32:shift|count[3]~266
--operation mode is normal

F1L83 = F1_count[5] # F1_count[1] # F1_count[0] # F1_count[3];


--F1L93 is shift32:shift|count[3]~267
--operation mode is normal

F1L93 = reset1 # !F1_count[2] & !F1_count[4] & !F1L83;


--F1L04 is shift32:shift|count[3]~268
--operation mode is normal

F1L04 = B1_en1 & !F1_flag & (reset1 # !B1_sel1);


--F1L31 is shift32:shift|add~236
--operation mode is arithmetic

F1L31_carry_eqn = F1L81;
F1L31 = F1_count1[2] $ (F1L31_carry_eqn);

--F1L41 is shift32:shift|add~238
--operation mode is arithmetic

F1L41 = CARRY(F1_count1[2] # !F1L81);


--F1L22 is shift32:shift|always1~0
--operation mode is normal

F1L22 = B1_en1 & (!F1_flag);


--F1L51 is shift32:shift|add~241
--operation mode is arithmetic

F1L51 = !F1_count1[0];

--F1L61 is shift32:shift|add~243
--operation mode is arithmetic

F1L61 = CARRY(F1_count1[0]);


--F1L71 is shift32:shift|add~246
--operation mode is arithmetic

F1L71_carry_eqn = F1L61;
F1L71 = F1_count1[1] $ (!F1L71_carry_eqn);

--F1L81 is shift32:shift|add~248
--operation mode is arithmetic

F1L81 = CARRY(!F1_count1[1] & (!F1L61));


--F1L91 is shift32:shift|add~251
--operation mode is normal

F1L91_carry_eqn = F1L12;
F1L91 = F1_count1[4] $ (F1L91_carry_eqn);


--F1L02 is shift32:shift|add~256
--operation mode is arithmetic

F1L02_carry_eqn = F1L41;
F1L02 = F1_count1[3] $ (!F1L02_carry_eqn);

--F1L12 is shift32:shift|add~258
--operation mode is arithmetic

F1L12 = CARRY(!F1_count1[3] & (!F1L41));


--F1L16 is shift32:shift|crc_reg[15]~252
--operation mode is normal

F1L16 = B1_en1 & !F1_flag & (B1_sel1 # reset1);


--F1_state.e3 is shift32:shift|state.e3
--operation mode is normal

F1_state.e3_lut_out = F1_crcout & F1_state.e2;
F1_state.e3 = DFFEAS(F1_state.e3_lut_out, clk, VCC, , B1_en1, , , , );


--B1L4 is control:control1|add~461
--operation mode is normal

B1L4 = B1_count2[1] & B1_count2[0] & (!B1_count2[3]);


--B1L13 is control:control1|count2[3]~204
--operation mode is normal

B1L13 = B1_reset2 # reset1 # !B1_en3 & B1_en2;


--B1L44 is control:control1|reset2~395
--operation mode is normal

B1L44 = B1L7 & !B1_count1[1] & !B1_count1[0] & B1_en1;


--B1_count3[3] is control:control1|count3[3]
--operation mode is normal

B1_count3[3]_lut_out = B1_count3[3] & (B1_count3[2] # B1_count3[1] # B1_count3[0]) # !B1_count3[3] & B1_count3[2] & B1_count3[1] & B1_count3[0];
B1_count3[3] = DFFEAS(B1_count3[3]_lut_out, clk, VCC, , B1L83, , , , );


--B1_count3[2] is control:control1|count3[2]
--operation mode is normal

B1_count3[2]_lut_out = B1L63 & !B1_count3[3] & (B1_count3[2] $ B1L5) # !B1L63 & B1_count3[2];
B1_count3[2] = DFFEAS(B1_count3[2]_lut_out, clk, VCC, , , , , , );


--B1_count3[1] is control:control1|count3[1]
--operation mode is normal

B1_count3[1]_lut_out = B1L63 & !B1_count3[3] & (B1_count3[1] $ B1_count3[0]) # !B1L63 & B1_count3[1];
B1_count3[1] = DFFEAS(B1_count3[1]_lut_out, clk, VCC, , , , , , );


--B1_count3[0] is control:control1|count3[0]
--operation mode is normal

B1_count3[0]_lut_out = B1_count3[0] & (B1_count3[3] & !B1L54 # !B1L83) # !B1_count3[0] & !B1_count3[3] & (B1L83);
B1_count3[0] = DFFEAS(B1_count3[0]_lut_out, clk, VCC, , , , , , );


--B1L54 is control:control1|reset2~396
--operation mode is normal

B1L54 = !B1_count3[2] & !B1_count3[1] & !B1_count3[0];


--B1L64 is control:control1|reset2~397
--operation mode is normal

B1L64 = B1_en3 & B1_count3[3] & B1L54;


--B1L52 is control:control1|count1[5]~337
--operation mode is normal

B1L52 = B1L42 & !B1L41 & (!B1_count1[4] # !B1_count1[5]);


--F1_state.e2 is shift32:shift|state.e2
--operation mode is normal

F1_state.e2_lut_out = F1_crcout & F1_state.e1;
F1_state.e2 = DFFEAS(F1_state.e2_lut_out, clk, VCC, , B1_en1, , , , );


--B1L83 is control:control1|count3[3]~8
--operation mode is normal

B1L83 = ept & B1_en3 & !B1_reset2 & !reset1;


--B1L5 is control:control1|add~462
--operation mode is normal

B1L5 = B1_count3[1] & B1_count3[0];


--B1L63 is control:control1|count3[2]~420
--operation mode is normal

B1L63 = B1L83 & (B1L54 # !B1_count3[3]);


--F1_state.e1 is shift32:shift|state.e1
--operation mode is normal

F1_state.e1_lut_out = F1_crcout & F1_state.e0;
F1_state.e1 = DFFEAS(F1_state.e1_lut_out, clk, VCC, , B1_en1, , , , );


--F1_state.e0 is shift32:shift|state.e0
--operation mode is normal

F1_state.e0_lut_out = !F1_state.e4 # !F1_crcout;
F1_state.e0 = DFFEAS(F1_state.e0_lut_out, clk, VCC, , B1_en1, , , , );


--B1L94 is control:control1|sel1~248
--operation mode is normal

B1L94 = B1_count1[2] & B1_count1[1] & B1_count1[0] & B1_count1[4];


--D1L5 is free:free1|count[2]~533
--operation mode is normal

D1L5 = D1_count[2] $ (!D1_count[3] & D1_count[1] & D1_count[0]);


--~GND is ~GND
--operation mode is normal

~GND = GND;


--ept is ept
--operation mode is input

ept = INPUT();


--clk is clk
--operation mode is input

clk = INPUT();


--reset1 is reset1
--operation mode is input

reset1 = INPUT();


--dout is dout
--operation mode is output

dout = OUTPUT(E1L2);


--dout1 is dout1
--operation mode is output

dout1 = OUTPUT(F1_crcout);


--dout2 is dout2
--operation mode is output

dout2 = OUTPUT(C1_dout);


--dout3 is dout3
--operation mode is output

dout3 = OUTPUT(D1_dout);


--dout4 is dout4
--operation mode is output

dout4 = OUTPUT(F1L86);


--din is din
--operation mode is output

din = OUTPUT(GND);


--flag is flag
--operation mode is output

flag = OUTPUT(F1_flag);


--en1 is en1
--operation mode is output

en1 = OUTPUT(B1_en1);


--en2 is en2
--operation mode is output

en2 = OUTPUT(B1_en2);


--en3 is en3
--operation mode is output

en3 = OUTPUT(B1_en3);


--sel1 is sel1
--operation mode is output

sel1 = OUTPUT(B1_sel1);


--sel2 is sel2
--operation mode is output

sel2 = OUTPUT(B1_sel2);


--sel3 is sel3
--operation mode is output

sel3 = OUTPUT(GND);


--clkout is clkout
--operation mode is output

clkout = OUTPUT(GND);