hdlc.fit.rpt

该工程是基于verilog hdl 语言编写的帧传输协议HDLC帧的发送端代码

; 8                                           ; 0                            ;
; 9                                           ; 0                            ;
; 10                                          ; 10                           ;
; 11                                          ; 1                            ;
+---------------------------------------------+------------------------------+


+--------------------------------------------------------------------------------+
; LAB Signals Sourced Out                                                        ;
+-------------------------------------------------+------------------------------+
; Number of Signals Sourced Out  (Average = 5.20) ; Number of LABs  (Total = 15) ;
+-------------------------------------------------+------------------------------+
; 0                                               ; 0                            ;
; 1                                               ; 3                            ;
; 2                                               ; 0                            ;
; 3                                               ; 2                            ;
; 4                                               ; 1                            ;
; 5                                               ; 1                            ;
; 6                                               ; 4                            ;
; 7                                               ; 0                            ;
; 8                                               ; 1                            ;
; 9                                               ; 2                            ;
; 10                                              ; 1                            ;
+-------------------------------------------------+------------------------------+


+----------------------------------------------------------------------------+
; LAB Distinct Inputs                                                        ;
+---------------------------------------------+------------------------------+
; Number of Distinct Inputs  (Average = 9.40) ; Number of LABs  (Total = 15) ;
+---------------------------------------------+------------------------------+
; 0                                           ; 0                            ;
; 1                                           ; 0                            ;
; 2                                           ; 2                            ;
; 3                                           ; 2                            ;
; 4                                           ; 0                            ;
; 5                                           ; 0                            ;
; 6                                           ; 0                            ;
; 7                                           ; 1                            ;
; 8                                           ; 1                            ;
; 9                                           ; 0                            ;
; 10                                          ; 3                            ;
; 11                                          ; 0                            ;
; 12                                          ; 1                            ;
; 13                                          ; 2                            ;
; 14                                          ; 2                            ;
; 15                                          ; 0                            ;
; 16                                          ; 0                            ;
; 17                                          ; 0                            ;
; 18                                          ; 0                            ;
; 19                                          ; 0                            ;
; 20                                          ; 1                            ;
+---------------------------------------------+------------------------------+


+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Sun Jul 01 22:51:44 2007
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off hdlc -c hdlc
Info: Selected device EP1C3T100C6 for design "hdlc"
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices. 
Info: No exact pin location assignment(s) for 17 pins of 17 total pins
    Info: Pin dout not assigned to an exact location on the device
    Info: Pin dout1 not assigned to an exact location on the device
    Info: Pin dout2 not assigned to an exact location on the device
    Info: Pin dout3 not assigned to an exact location on the device
    Info: Pin dout4 not assigned to an exact location on the device
    Info: Pin din not assigned to an exact location on the device
    Info: Pin flag not assigned to an exact location on the device
    Info: Pin en1 not assigned to an exact location on the device
    Info: Pin en2 not assigned to an exact location on the device
    Info: Pin en3 not assigned to an exact location on the device
    Info: Pin sel1 not assigned to an exact location on the device
    Info: Pin sel2 not assigned to an exact location on the device
    Info: Pin sel3 not assigned to an exact location on the device
    Info: Pin clkout not assigned to an exact location on the device
    Info: Pin ept not assigned to an exact location on the device
    Info: Pin clk not assigned to an exact location on the device
    Info: Pin reset1 not assigned to an exact location on the device
Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements
    Info: Assuming a global fmax requirement of 1 MHz
    Info: Not setting a global tsu requirement
    Info: Not setting a global tco requirement
    Info: Not setting a global tpd requirement
Info: Performing register packing on registers with non-logic cell location assignments
Info: Completed register packing on registers with non-logic cell location assignments
Info: Completed User Assigned Global Signals Promotion Operation
Info: DQS I/O pins require 0 global routing resources.
Info: Automatically promoted signal "clk" to use Global clock in PIN 10
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Started Fast Input/Output/OE register processing
Info: Finished Fast Input/Output/OE register processing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density
Info: Finished moving registers into I/O cells, LUTs, and RAM blocks
Info: Finished register packing
Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
    Info: Number of I/O pins in group: 16 (unused VREF, 3.30 VCCIO, 2 input, 14 output, 0 bidirectional)
        Info: I/O standards used: LVTTL.
Info: I/O bank details before I/O pin placement
    Info: Statistics of I/O banks
        Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 3 total pin(s) used --  11 pins available
        Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  17 pins available
        Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  17 pins available
        Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  17 pins available
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Estimated most critical path is register to register delay of 5.762 ns
    Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X20_Y6; Fanout = 7; REG Node = 'control:control1|count1[1]'
    Info: 2: + IC(0.890 ns) + CELL(0.225 ns) = 1.115 ns; Loc. = LAB_X20_Y7; Fanout = 1; COMB Node = 'control:control1|always0~267'
    Info: 3: + IC(0.286 ns) + CELL(0.225 ns) = 1.626 ns; Loc. = LAB_X20_Y7; Fanout = 4; COMB Node = 'control:control1|always0~268'
    Info: 4: + IC(0.171 ns) + CELL(0.340 ns) = 2.137 ns; Loc. = LAB_X20_Y7; Fanout = 4; COMB Node = 'control:control1|always0~11'
    Info: 5: + IC(0.716 ns) + CELL(0.340 ns) = 3.193 ns; Loc. = LAB_X20_Y6; Fanout = 14; COMB Node = 'control:control1|en1'
    Info: 6: + IC(0.057 ns) + CELL(0.454 ns) = 3.704 ns; Loc. = LAB_X20_Y6; Fanout = 2; COMB Node = 'control:control1|count1[5]~336'
    Info: 7: + IC(0.057 ns) + CELL(0.454 ns) = 4.215 ns; Loc. = LAB_X20_Y6; Fanout = 6; COMB Node = 'control:control1|count1[5]~337'
    Info: 8: + IC(0.880 ns) + CELL(0.667 ns) = 5.762 ns; Loc. = LAB_X20_Y7; Fanout = 3; REG Node = 'control:control1|count1[3]'
    Info: Total cell delay = 2.705 ns ( 46.95 % )
    Info: Total interconnect delay = 3.057 ns ( 53.05 % )
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Fitter routing operations beginning
Info: Fitter routing operations ending: elapsed time is 00:00:00
Info: Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.
Info: Completed Fixed Delay Chain Operation
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Info: Completed Auto Delay Chain Operation
Warning: The following 3 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results
    Info: Pin din has GND driving its datain port
    Info: Pin sel3 has GND driving its datain port
    Info: Pin clkout has GND driving its datain port
Info: Quartus II Fitter was successful. 0 errors, 1 warning
    Info: Processing ended: Sun Jul 01 22:51:48 2007
    Info: Elapsed time: 00:00:05