stop.v

来自「verilog实现」· Verilog 代码 · 共 30 行

module stop(inenable,infifo,reg_sp,clksp,in_sp);
   output inenable;
   output [7:0] infifo;
   output [7:0] reg_sp;
   input clksp;
   input in_sp;
   reg [7:0] infifo;
   reg [7:0] reg_sp;
   reg [4:0] i;
   reg inenable;
   
   initial begin
      i=4'b0000;
      reg_sp=8'b00000000;
   end
   
   always@(posedge clksp)
      begin 
        if (i==4'b1000) begin
          infifo[7:0]=reg_sp[7:0];
          inenable=1;
          i=4'b0000;
        end
        else inenable=0;
        reg_sp=reg_sp>>1;
        reg_sp[7]=in_sp;
        i=i+1;
      end
endmodule