ptos.v

来自「verilog实现」· Verilog 代码 · 共 31 行

module ptos(outenable,out_ps,reg_ps,outfifo,clkps);
   output outenable;
   output out_ps;
   output [7:0] reg_ps;
   input [7:0] outfifo;
   input clkps;
   reg out_ps;
   reg [7:0] reg_ps;
   reg [4:0] i;
   reg outenable;
   
   initial begin
      i=4'b0000;
      reg_ps=8'b00000000;
   end
   
   always@(posedge clkps)
      begin 
         if (i==0) begin
            i=8;
            outenable=1;
            reg_ps=outfifo;
         end      
         else outenable=0;
         out_ps=reg_ps[0];
         reg_ps=reg_ps>>1;
         i=i-1;
      end
endmodule