test.v

来自「verilog实现」· Verilog 代码 · 共 34 行

module test_7;
 // Signal declaration
	reg clkps;
	reg  [7:0] outfifo;
	wire [7:0] reg_ps;
	wire out_ps;	

// MUX instance
        ptos exam(out_ps,reg_ps,outfifo,clkps);
// Apply Stimulus

initial  
begin
  clkps=0;
  outfifo=8'b11001110;
end

always 
begin
   #5 clkps=0;
   #5 clkps=1;
end

initial fork
#88 outfifo=8'b01011110;
#162  $finish;   // finish simulation
join
// Display Results
 
initial  // print all changes to all signal values
  $monitor($time, " outfifo=%b,out_ps=%b,reg_ps=%b",outfifo,out_ps,reg_ps);

endmodule