testall.v

来自「verilog实现」· Verilog 代码 · 共 57 行

module test_7;
 // Signal declaration
	reg clksp,in_sp;
	wire [7:0] infifo,reg_sp;
	reg clkps;
	reg  [7:0] outfifo;
	wire [7:0] reg_ps;
	wire out_ps,inenable,outenable;	

// MUX instance
        stop exam_stop(inenable,infifo,reg_sp,clksp,in_sp);
        fifo exam_fifo(outfifo,infifo,inenable,outenable);
        ptos exam_ptos(outenable,out_ps,reg_ps,outfifo,clkps);
// Apply Stimulus

initial  
begin
  clkps=0;
  clksp=0;
  in_sp=0;
end

always 
fork
   #5 clksp=0;
   #5 clksp=1;
   #10 clkps=0;
   #10 clkps=1;   
join

initial fork
#8  in_sp=0;
#18 in_sp=1;
#28 in_sp=1;
#38 in_sp=1;
#48 in_sp=0;
#58 in_sp=0;
#68 in_sp=1;
#78 in_sp=1;//11001110
#88 in_sp=1;
#98 in_sp=0;
#108 in_sp=0;
#118 in_sp=0;
#128 in_sp=1;
#138 in_sp=1;
#148 in_sp=0;
#158 in_sp=0;//01100011
#162  $finish;   // finish simulation
join
// Display Results
 
initial  // print all changes to all signal values
  $monitor($time, " in_sp=%b out_sp=%b ",in_sp,out_ps);

endmodule