fifo.v

来自「verilog实现」· Verilog 代码 · 共 24 行

module fifo(outfifo,infifo,inenable,outenable);
   output [7:0] outfifo;
   input [7:0] infifo;
   input inenable,outenable;
   reg [7:0] outfifo;
   reg [63:0] reg_fifo;
   parameter  pointer=0;
   
   
   always @(inenable or outenable) begin
      if (outenable) begin
         outfifo=reg_fifo[7:0];
         reg_fifo=reg_fifo>>8;
         pointer=pointer-8;
      end
      if (inenable) begin
         reg_fifo[pointer+7:pointer]=infifo;
         pointer=pointer+8;
      end
   end
endmodule