test_7.v

来自「verilog实现」· Verilog 代码 · 共 49 行

module test_7;
 // Signal declaration
	reg clksp,in_sp;
	wire [7:0] infifo,reg_sp;


// MUX instance
        stop exam(infifo,reg_sp,clksp,in_sp);
// Apply Stimulus

initial  
begin
  clksp=0;
  in_sp=0;
end

always 
begin
   #5 clksp=0;
   #5 clksp=1;
end

initial fork
#8  in_sp=0;
#18 in_sp=1;
#28 in_sp=1;
#38 in_sp=1;
#48 in_sp=0;
#58 in_sp=0;
#68 in_sp=1;
#78 in_sp=1;//11001110
#88 in_sp=1;
#98 in_sp=0;
#108 in_sp=0;
#118 in_sp=0;
#128 in_sp=1;
#138 in_sp=1;
#148 in_sp=0;
#158 in_sp=0;//01100011
#162  $finish;   // finish simulation
join
// Display Results
 
initial  // print all changes to all signal values
  $monitor($time, " infifo=%b,in_sp=%b,reg_sp=%b",infifo,in_sp,reg_sp);

endmodule