top.v

I2C的slave端程序,用于响应master端,并进行通信

`timescale 1 ps / 1 ps
module top(
            clk,
            reset,
            scl,
            ackl,
            sda
            );
input clk,reset,scl,ackl;
inout sda;

  wire data_ser_in, sel_sda_in, sel_sda_out, enable, data_out; 
//reg data_ser_in, sel_sda_in, sel_sda_out, enable, data_out; 
//reg[7:0] data_par_in;

wire cnt_8;

//reg [2:0] ct;

wire[2:0] ct;

//reg[7:0] data0;
 wire [7:0] data0;
//the following sentence added by me
 wire [7:0] data_par_out;
 wire add; 
 
reg en_cnt;
wire start,start_1;

register     r0(.clk(clk),
                .reset(reset),
		.data_par_out(data_par_out),
		.data_ser_in(data_ser_in),
		.scl(scl),
		.add(add),
		.start(start),
		.cnt_8(cnt_8),
		.ackl(ackl),
                .sel_sda_in(sel_sda_in),
		.sel_sda_out(sel_sda_out),

		.start_1(start_1),

		.load(load),
		.data_o(data_out),
		.en(enable), 
		.clear(clear),
		.data_par_in(data0),
		.data_ser_out(data_ser_out)
		);

bustri1 b1(
	.data(data_out),
	.enabledt(sel_sda_in),
	.enabletr(sel_sda_out),
	.tridata(sda),
	.result(data_ser_in)
	);
cnt8 c0(.clk(scl),
        .reset(reset),
	.clear(clear),
	.cnt(ct),
	.en_cnt(cnt_8)
	);
cnt_a c1(reset,start,aclr);
cnt_e c2(add, cnt_8, cnt_en);
lpm_counter0 count0(
	            .clock(scl),
     		    .cnt_en(enable),
 	 	    .sclr(clear),
	           	.aclr(reset),
  	           	.q(ct)
  	           	);
lpm_counter1 count1(
		    .clock(scl),
		    .cnt_en(cnt_en),
	           	.aclr(aclr),
	           	.q(add)
	           	); 
shiftreg shift0(
	.clock(scl),
	.enable(enable),
	.shiftin(data_ser_in),
	.load(load),
	.aclr(reset),
	.data(data0),
	.q(data_par_out),
	.shiftout(data_ser_out)
	);
sync sy0(
        .dstb(start_1),
        .x2(start),
        .clk2(clk),
        .rstb(reset)
        );	
        
endmodule