lpm_counter0.v

来自「I2C的slave端程序,用于响应master端,并进行通信」· Verilog 代码 · 共 47 行

// synopsys translate_off

// synopsys translate_on
`timescale 1 ps / 1 ps
module lpm_counter0 (
	clock,
	cnt_en,
	sclr,
	aclr,
	q);

	input	  clock;
	input	  cnt_en;
	input	  sclr;
	input	  aclr;
	output	[2:0]  q;

	wire [2:0] sub_wire0;
	wire [2:0] q = sub_wire0[2:0];

	lpm_counter	lpm_counter_component (
				.sclr (sclr),
				.aclr (aclr),
				.clock (clock),
				.cnt_en (cnt_en),
				.q (sub_wire0)
				// synopsys translate_off
				,
				.cout (),
				.sload (),
				.aload (),
				.eq (),
				.updown (),
				.clk_en (),
				.cin (),
				.data (),
				.sset (),
				.aset ()
				// synopsys translate_on
				);
	defparam
		lpm_counter_component.lpm_width = 3,
		lpm_counter_component.lpm_type = "LPM_COUNTER",
		lpm_counter_component.lpm_direction = "UP";


endmodule