bustri1.v

来自「I2C的slave端程序,用于响应master端,并进行通信」· Verilog 代码 · 共 35 行

// synopsys translate_off

// synopsys translate_on
`timescale 1 ps / 1 ps
module bustri1 (
	data,
	enabledt,
	enabletr,
	tridata,
	result);

	input	  data;
	input	  enabledt;
	input	  enabletr;
	inout	[0:0]  tridata;
	output	  result;

	wire [0:0] sub_wire0;
	wire [0:0] sub_wire1 = sub_wire0[0:0];
	wire  result = sub_wire1;
	wire  sub_wire2 = data;
	wire  sub_wire3 = sub_wire2;

	lpm_bustri	lpm_bustri_component (
				.tridata (tridata),
				.enabletr (enabletr),
				.enabledt (enabledt),
				.data (sub_wire3),
				.result (sub_wire0));
	defparam
		lpm_bustri_component.lpm_width = 1,
		lpm_bustri_component.lpm_type = "LPM_BUSTRI";


endmodule