sync.v

来自「I2C的slave端程序,用于响应master端,并进行通信」· Verilog 代码 · 共 30 行

/***********************************************************
file:		sync.v
authors:	Bernardo Mota
-------->   sync 12: slow - fast
***********************************************************/
`timescale 1 ps / 1 ps
module sync (dstb, x2, clk2, rstb);

input	dstb, rstb, clk2;
output	x2;
reg	    r1, r2;
wire	x2;

always@(posedge clk2 or negedge rstb)

if(!rstb)
	begin
		r1 = 0;
		r2 = 0;
	end
else		
	begin
		r1 <= dstb;
		r2 <= r1;
	end

assign x2 = ~(~r1 | r2);

endmodule