shiftreg.v

来自「I2C的slave端程序,用于响应master端,并进行通信」· Verilog 代码 · 共 52 行

// synopsys translate_off

// synopsys translate_on
`timescale 1 ps / 1 ps
module shiftreg (
	clock,
	enable,
	shiftin,
	load,
	aclr,
	data,
	q,
	shiftout);

	input	  clock;
	input	  enable;
	input	  shiftin;
	input	  load;
	input	  aclr;
	input	[7:0]  data;
	output	[7:0]  q;
	output	  shiftout;

	wire [7:0] sub_wire0;
	wire  sub_wire1;
	wire [7:0] q = sub_wire0[7:0];
	wire  shiftout = sub_wire1;

	lpm_shiftreg	lpm_shiftreg_component (
				.enable (enable),
				.load (load),
				.aclr (aclr),
				.clock (clock),
				.data (data),
				.shiftin (shiftin),
				.q (sub_wire0),
				.shiftout (sub_wire1)
				// synopsys translate_off
				,
				.sclr (),
				.aset (),
				.sset ()
				// synopsys translate_on
				);
	defparam
		lpm_shiftreg_component.lpm_type = "LPM_SHIFTREG",
		lpm_shiftreg_component.lpm_width = 8,
		lpm_shiftreg_component.lpm_direction = "LEFT";


endmodule