cnt8.v

来自「I2C的slave端程序,用于响应master端,并进行通信」· Verilog 代码 · 共 75 行

/**********************************************************************
file:		 cnt8.v
authors:     Carmen Gonzalez
creation:	 00.00.03
last update: 01.09.03
summary:     keep the signal en_cnt (cnt = 8) high until clear is high
**********************************************************************/
`timescale 1 ps / 1 ps
module cnt8 (clk,
             reset,
			 clear,
			 cnt,
			 en_cnt);
			 
input clk;
input reset;
input clear;
//input [3:0] cnt;
input [2:0] cnt;


output en_cnt;

wire cnt_8;
reg en_cnt;


//assign cnt_8 = (cnt[3]&~cnt[2]&~cnt[1]&~cnt[0]);

assign cnt_8 = (~cnt[2]&~cnt[1]&~cnt[0]);

reg st;
reg nx_st;

parameter s0 = 1'b0;
parameter s1 = 1'b1;


always @ (posedge clk or negedge reset)
begin
	if (~reset)
		st <= s0;
	else
		st <= nx_st;
end

always @ (st or cnt_8 or clear)
begin
nx_st = st;
	
	case (st)
	
	s0:
		begin
		en_cnt = 1'b0;
		if (cnt_8)
			nx_st = s1;
		else
			nx_st = s0;
		end
		
	s1:
		begin
		en_cnt = 1'b1;
		if (clear)
			nx_st = s0;
		else
			nx_st = s1;
		end
	endcase
end
		
endmodule