register.v

I2C的slave端程序,用于响应master端,并进行通信

/***********************************************************
		             register.v
************************************************************
file:		register.v
authors:	Feifei Zou
creation:	28.04.05
last update 03.05.05
***********************************************************/
`timescale 1 ps / 1 ps
module register(clk,
                reset,
		data_par_out,
		data_ser_in,
		scl,
		add,
		start,
		cnt_8,
		ackl,
                sel_sda_in,
		sel_sda_out,
		/*data,*/
		start_1,
		load,
		data_o,
		en, 
		clear,
		data_par_in,
		data_ser_out
		);
//I/O 
input clk,reset,scl;
input [7:0] data_par_out;
input add,start,data_ser_in,data_ser_out;
input cnt_8;
input ackl;
output sel_sda_in;
output sel_sda_out;
output start_1;
output load;
output data_o;
output en;
output clear;
output [7:0] data_par_in;
/*output data;*/

//reg define
reg [7:0] data_par_in;
/*reg [7:0] data_par_out;*/
reg rw;
reg start_1;
reg load;
reg sel_sda_in;
reg sel_sda_out;
reg en;
reg clear;
reg data_o;
reg ACK;
/*reg data_ser_in;*/
/*reg data;*/
reg [2:0] st;
reg [2:0] nx_st;

assign TMS_ALTRO=4'b1111;
//States definition
parameter idle        = 3'b000, // 0 
		  str         = 3'b001, // 1
		  wait_add    = 3'b010, // 2
		  latch_add   = 3'b011, // 3	
		  rw_data     = 3'b100, // 4
		  data_out    = 3'b101, // 5
		  data_in     = 3'b110; // 6
		  
always@(posedge clk or negedge reset)
 begin:statereg
	if (~reset)
		st <= idle;
	else
		st <= nx_st;
		
end
   
always @(scl or st or data_ser_in or add or start or rw or ACK or cnt_8)
begin
  nx_st=st;
 
  case(st)
 
   idle: //0
		begin
		rw=1'b0;
		sel_sda_in=1'b1;
      	sel_sda_out=1'b0;
      	start_1=1'b0;
      	data_o=1'b0;
        clear=1'b1;
		en=1'b0;
	  
	    if(scl&~data_ser_in)
			nx_st=str;
      	else if(scl&data_ser_in)
 			nx_st=idle;
		end
   	
	str: //1
	  	begin
		start_1=1'b1;
      	en=1'b1;
      	clear=1'b0;  
        
		if(~scl)
			nx_st=wait_add;
		else 
		    nx_st=str;
		end
   	
	wait_add: //2
        begin
		start_1=1'b1;
		en=1'b1;
		clear=1'b0;
		sel_sda_in=1'b1;
		sel_sda_out=1'b0;
		
		/*if(~scl)
			data=data_ser_in;
		else
			data=data;             ???????????????sda??????????? */
					
		if(start&add)
		    nx_st=latch_add;
		else if(start&~add)
		    nx_st=rw_data;
		end
		
	latch_add: //3
		begin
		start_1=1'b1;
		en=1'b1;
		clear=1'b0;
		load=1'b1;
		rw=data_par_out[7];
		
		if(rw)
			begin
			sel_sda_in=1'b0;
			sel_sda_out=1'b1;
			data_o=1'b0;		   
			
			nx_st=data_out;
			end
		else 
			begin
			sel_sda_in=1'b0;
			sel_sda_out=1'b1;
			data_o=1'b0;
			nx_st=data_in;
			end
		end
		
	rw_data: //4
	    begin
		start_1=1'b1;
	    en=1'b1;
		clear=1'b0;
		
		if(rw)
			nx_st=data_out;
		else 
			nx_st=data_in;
		end
			
	data_out: //5
	    begin
		start_1=1'b1;
		en=1'b1;
		clear=1'b0;
		load=1'b0;
		sel_sda_in=1'b0;
		sel_sda_out=1'b1;
		
		if(~scl)
			data_o=data_ser_out;  /*????????sel_sda_out?0?1????*/
		else if(scl)
			data_o=data_o;
        else if(cnt_8)
			begin
			/*ACK=ackl;*/
			en=1'b0;
			sel_sda_in=1'b1;
			sel_sda_out=1'b0;
			ACK=data_ser_in;	
				if(ACK)
				nx_st=data_out;
				else 
				nx_st=idle;
		    end
		else if(~cnt_8)
			nx_st=data_out;
		end
		
	data_in: //6
		begin
		start_1=1'b1;
		en=1'b1;
		clear=1'b0;
		load=1'b1;
		sel_sda_in=1'b1;
		sel_sda_out=1'b0;
		
		/*if(~scl)
			data=data_ser_in;
		else if(scl)
			data=data;
		else*/
		 if(cnt_8)
			begin
			ACK=ackl;
			sel_sda_in=1'b0;
			sel_sda_out=1'b1;
			
				if(ACK)
					begin
					data_o=1'b0;
					nx_st=data_in;
					end
				else 
					begin
					data_o=1'b1;
					nx_st=idle;
					end
			end
		else if(~cnt_8)
			nx_st=data_in;
		end
    
	default:
			begin
			clear        = 1'b1;
			en           = 1'b0;
			load         = 1'b0;
			rw=1'b0;
			sel_sda_in=1'b0;
      		sel_sda_out=1'b0;
      		start_1=1'b0;
      		data_o=1'b0;
        	nx_st        = idle;
			end 
	endcase
end


/*always @ (posedge clk or negedge reset)
begin
	if (~reset)
		begin
		data=1'b0;
		data_par_in[7:0] = 8'b0;
		end
	else  
		data=data;
end*/
		
endmodule