_primary.vhd

来自「一个完整的MIPS CPU」· VHDL 代码 · 共 32 行

library verilog;
use verilog.vl_types.all;
entity decode is
    port(
        clk             : in     vl_logic;
        reset           : in     vl_logic;
        jmp_en          : in     vl_logic;
        jmp_en_d        : in     vl_logic;
        code_d          : in     vl_logic_vector(31 downto 0);
        reg_write_en_dd : out    vl_logic;
        reg_write_en_ddd: out    vl_logic;
        reg_write_en_dddd: out    vl_logic;
        mem_write_en_dd : out    vl_logic;
        mem_write_en_ddd: out    vl_logic;
        is_jmp_dd       : out    vl_logic;
        is_jmp_ddd      : out    vl_logic;
        is_jeq_dd       : out    vl_logic;
        is_jeq_ddd      : out    vl_logic;
        is_jne_dd       : out    vl_logic;
        is_jne_ddd      : out    vl_logic;
        exe_result_sel_dd: out    vl_logic_vector(2 downto 0);
        exe_result_sel_ddd: out    vl_logic_vector(2 downto 0);
        pre_exe_result_sel_dd: out    vl_logic_vector(2 downto 0);
        pre_exe_result_sel_ddd: out    vl_logic_vector(2 downto 0);
        exe_data1_sel_dd: out    vl_logic;
        exe_data2_sel_dd: out    vl_logic_vector(1 downto 0);
        reg_result_address_sel_dd: out    vl_logic_vector(1 downto 0);
        exe_address1_sel_dd: out    vl_logic_vector(1 downto 0);
        exe_address2_sel_dd: out    vl_logic
    );
end decode;