_primary.vhd

来自「一个完整的MIPS CPU」· VHDL 代码 · 共 25 行

library verilog;
use verilog.vl_types.all;
entity execute is
    port(
        clk             : in     vl_logic;
        reset           : in     vl_logic;
        exe_data1_ddd   : in     vl_logic_vector(31 downto 0);
        exe_data2_ddd   : in     vl_logic_vector(31 downto 0);
        exe_address1_ddd: in     vl_logic_vector(15 downto 0);
        exe_address2_ddd: in     vl_logic_vector(15 downto 0);
        mem_write_en_ddd: in     vl_logic;
        is_jmp_ddd      : in     vl_logic;
        is_jeq_ddd      : in     vl_logic;
        is_jne_ddd      : in     vl_logic;
        exe_result_sel_ddd: in     vl_logic_vector(2 downto 0);
        pre_exe_result_sel_ddd: in     vl_logic_vector(2 downto 0);
        pc_current_dd   : in     vl_logic_vector(15 downto 0);
        address_out     : out    vl_logic_vector(15 downto 0);
        exe_result      : out    vl_logic_vector(31 downto 0);
        exe_result_dddd : out    vl_logic_vector(31 downto 0);
        jmp_en          : out    vl_logic;
        io_out          : out    vl_logic_vector(31 downto 0)
    );
end execute;