_primary.vhd

来自「一个完整的MIPS CPU」· VHDL 代码 · 共 16 行

library verilog;
use verilog.vl_types.all;
entity fetch is
    port(
        clk             : in     vl_logic;
        reset           : in     vl_logic;
        jmp_en          : in     vl_logic;
        address_jmp     : in     vl_logic_vector(15 downto 0);
        code_d          : out    vl_logic_vector(31 downto 0);
        code_dd         : out    vl_logic_vector(31 downto 0);
        pc_current_d    : out    vl_logic_vector(15 downto 0);
        pc_current_dd   : out    vl_logic_vector(15 downto 0);
        jmp_en_d        : out    vl_logic
    );
end fetch;