_primary.vhd

来自「一个完整的MIPS CPU」· VHDL 代码 · 共 16 行

library verilog;
use verilog.vl_types.all;
entity registers is
    port(
        clk             : in     vl_logic;
        write_en        : in     vl_logic;
        reset           : in     vl_logic;
        read_address1   : in     vl_logic_vector(4 downto 0);
        read_address2   : in     vl_logic_vector(4 downto 0);
        write_address   : in     vl_logic_vector(4 downto 0);
        write_data      : in     vl_logic_vector(31 downto 0);
        read_data1      : out    vl_logic_vector(31 downto 0);
        read_data2      : out    vl_logic_vector(31 downto 0)
    );
end registers;