_primary.vhd

来自「一个完整的MIPS CPU」· VHDL 代码 · 共 14 行

library verilog;
use verilog.vl_types.all;
entity data_memory is
    port(
        clk             : in     vl_logic;
        reset           : in     vl_logic;
        write_en        : in     vl_logic;
        address         : in     vl_logic_vector(15 downto 0);
        data_write      : in     vl_logic_vector(31 downto 0);
        data_read       : out    vl_logic_vector(31 downto 0);
        io_out          : out    vl_logic_vector(31 downto 0)
    );
end data_memory;