_primary.vhd

来自「一个完整的MIPS CPU」· VHDL 代码 · 共 30 行

library verilog;
use verilog.vl_types.all;
entity control is
    port(
        clk             : in     vl_logic;
        reset           : in     vl_logic;
        code_dd         : in     vl_logic_vector(31 downto 0);
        pc_current_dd   : in     vl_logic_vector(15 downto 0);
        exe_data1_sel_dd: in     vl_logic;
        exe_data2_sel_dd: in     vl_logic_vector(1 downto 0);
        exe_address1_sel_dd: in     vl_logic_vector(1 downto 0);
        exe_address2_sel_dd: in     vl_logic;
        reg_result_address_sel_dd: in     vl_logic_vector(1 downto 0);
        reg_result_next : in     vl_logic_vector(31 downto 0);
        reg_write_en_ddd: in     vl_logic;
        reg_result_dddd : in     vl_logic_vector(31 downto 0);
        reg_write_en_dddd: in     vl_logic;
        data_reg1       : in     vl_logic_vector(31 downto 0);
        data_reg2       : in     vl_logic_vector(31 downto 0);
        address_reg1    : out    vl_logic_vector(4 downto 0);
        address_reg2    : out    vl_logic_vector(4 downto 0);
        exe_data1_ddd   : out    vl_logic_vector(31 downto 0);
        exe_data2_ddd   : out    vl_logic_vector(31 downto 0);
        exe_address1_ddd: out    vl_logic_vector(15 downto 0);
        exe_address2_ddd: out    vl_logic_vector(15 downto 0);
        reg_result_address_ddd: out    vl_logic_vector(4 downto 0);
        reg_result_address_dddd: out    vl_logic_vector(4 downto 0)
    );
end control;