代码搜索结果
找到约 10,000 项符合
V 的代码
virtexe.v
module BSCAN_VIRTEX(TDO1, TDO2, TDI, RESET, SHIFT, UPDATE, SEL1, DRCK1, SEL2, DRCK2); // synthesis syn_black_box
input TDO1;
input TDO2;
output TDI;
output RESET;
output SHIFT;
output UPDATE;
o
virtex.v
module BSCAN_VIRTEX(TDO1, TDO2, TDI, RESET, SHIFT, UPDATE, SEL1, DRCK1, SEL2, DRCK2); // synthesis syn_black_box
input TDO1;
input TDO2;
output TDI;
output RESET;
output SHIFT;
output UPDATE;
o
sdrm.v
/******************************************************************************
*
* File Name: sdrm.v
* Version: 1.14
* Date: Sept 9, 1999
* Description: Top level module
* Depend
alu.v
module alu(clk, a, b, opcode, outp);
input clk;
input [7:0] a, b;
input [2:0] opcode;
output [7:0] outp;
reg [7:0] outp;
always @(posedge clk)
begin
case (opcode) /* synthesis full_c
module_a.v
module module_a ( CLK_TOP, B2A_IN, TOP2A_IN, C2A_IN, MODA_DATA,
MODA_CLK, MODA_OUT, A2B_OUT, A2TOP_OBUFT_I_OUT, A2C_OUT);
input CLK_TOP ;
input B2A_IN ;
input TOP2A_IN ;
input C2A_IN ;
top.v
module top (ipad_dll_clk_in, dll_rst,
top2a_c, top2b,
obuft_out, mod_c_out,
moda_data, moda_clk_pad, moda_out,
modb_data, modb_clk_pad, modb_out,
modc_data, modc_clk_pad, modc
tenths.v
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used *
* solely for design, simulation,
decode.v
module decode (binary,one_hot);
input [3:0] binary;
output[9:0] one_hot;
reg [9:0] one_hot;
always @(binary)
begin
case (binary)
4'b0001 : one_hot = 10'b0000000001; //1
4'b0010 : on
tenths.v
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used *
* solely for design, simulation,
decode.v
module decode (binary,one_hot);
input [3:0] binary;
output[9:0] one_hot;
reg [9:0] one_hot;
always @(binary)
begin
case (binary)
4'b0001 : one_hot = 10'b0000000001; //1
4'b0010 : on